During a process for producing a semiconductor integrated circuit, a wafer is exposed to light, then etched, then coated (plated), and then polished. This process is repeated until a layered structure is built up, and thus a desired circuit is produced. For high productivity during the process, two or more semiconductor integrated circuits are formed on one wafer at the same time.
One recent demand is to increase the number of circuits fabricated at the same time by increasing the diameter of the wafers. However, as the area of a wafer increases, it becomes more difficult to process a central section and a peripheral section of the wafer uniformly. Moreover, as smaller circuits are developed, highly accurate processing is required.
For example, with copper wiring, which is the recent mainstay of the field, a trench for wiring is formed on an insulator and then the insulator is plated with copper so that the trench is filled with copper. This plating method is called electro-chemical plating (ECP). Because not only the trench but also the entire insulator is plated with copper, the wafer is then polished using chemical mechanical polishing (CMP) so as to reveal the wiring pattern.
If large differences in height are formed on a wafer after CMP, things such as variations in the height of copper wires and excess copper cause short circuits. This decreases the performance and the yield rate.
The CMP removal rate is different depending on the material. For example, the removal rate of a copper wire is higher than the removal rate of an insulating layer. To suppress variations in height after CMP, it is important to maintain a uniform wire density. The wire density is the percentage area of a chip taken up by wiring. The wire density is also called “metal density” because wires are made of metal. Variations in height after CMP are also affected by the peripheral length of the wire.
Dummy metal fill for filling dummy metal (dummy wire) is a well-known technology for maintaining a uniform wire density and a uniform peripheral wire length. An area having a low wire density is filled with dummy metal in such a manner that the dummy metal is electrically disconnected from the real wire. Dummy metal cannot work as an electrical wire; therefore, dummy metal makes it possible to adjust the wire density and the peripheral wire length so that the CMP removal amount is adjusted to an appropriate value without affecting the operation of a circuit made up of real wires.
As smaller circuit layouts are developed, the amount of dummy metal data is increased and, therefore, filling with dummy metal in a regular pattern is required. Moreover, to suppress variation in the volume component of layered wire, it is preferable to arrange dummy metal in a pattern staggered with respect to the direction in which a wire object extends (in a zigzag pattern). A wire object, herein, is a metal area that is connected to another wire object and works as a part of an electric circuit. For example, a wire object having a narrow width works as a resistor and a pair of wire objects with an insulator between them works as a capacitor. A wire object is designed to have a given position specified by reference directions or XY directions. A reference direction for a wire object layout is the direction in which a wire object extends.
A dedicated dummy-metal-fill tool makes it possible to arrange dummy metal in a pattern staggered with respect to the direction in which a wire object extends. After the dummy metal is filled, it is checked whether the wire density and the peripheral wire length satisfy the circuit design criteria using a different tool. Therefore, a loop of dummy fill and layout checking is created, which increases the time taken to set a proper dummy layout.
Patent Document 1: Japanese Laid-open Patent Publication No. 11-265866
Patent Document 2: Japanese Laid-open Patent Publication No. 2006-060051
Patent Document 3: Japanese Laid-open Patent Publication No. 2000-340568
Patent Document 4: Japanese Laid-open Patent Publication No. 09-115905
Patent Document 5: Japanese Laid-open Patent Publication No. 2005-222214
Patent Document 6: Japanese Laid-open Patent Publication No. 2007-011729